Implementation and Evaluation of Two Independent Ising Machines on Same FPGA Board by Reducing Number of Interactions Inside Ising Machine

被引:0
作者
Kitahara, Shinjiro [1 ]
Megumi, Taichi [1 ]
Endo, Akari [1 ]
Kawahara, Takayuki [1 ]
机构
[1] Tokyo Univ Sci, Dept Elect Engn, Katsushika, Tokyo 1258585, Japan
来源
IEEE ACCESS | 2024年 / 12卷
基金
日本学术振兴会;
关键词
Optimization; Annealing; Field programmable gate arrays; Simulated annealing; Program processors; Periodic structures; Mathematical models; Couplings; Stationary state; Hardware; annealing processor; FPGA implementation; interaction reduction; Ising machine; simulated annealing;
D O I
10.1109/ACCESS.2024.3471695
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The development of annealing processors has progressed as a solution to large-scale combinatorial optimization problems. Inside a fully-coupled annealing machine that can handle a wide range of combinatorial optimization problems, there are elements called interactions that indicate the force between spins, the number of which is the square of the number of spins. However, the area of the circuit is greatly restricted. Therefore, we focus on the symmetry of interactions and propose a method for reducing the number of interactions by giving regularity to the two-dimensional arrangement of interactions. The interaction halving method has a high affinity with the previously published scalable fully-coupled annealing machine, and the interaction proposed this time for the 384-spin full-coupled annealing machine using 16 Field Programmable Gate Array chips shown in previous research. By applying the reduction method, we succeeded in implementing two independent 384-spin fully coupled annealing machines with 16 chips.
引用
收藏
页码:145530 / 145539
页数:10
相关论文
共 8 条
  • [1] Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins
    Iimura, Ryoma
    Kitamura, Satoshi
    Kawahara, Takayuki
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 68 (12) : 5061 - 5071
  • [2] Kitahara S., 2022, P IEEE AS SOL STAT C, P3
  • [3] A 144Kb Annealing System Composed of 9x16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
    Takemoto, Takashi
    Yamamoto, Kasho
    Yoshimura, Chihiro
    Hayashi, Masato
    Tada, Masafumi
    Saito, Hiroaki
    Mashimo, Mayumi
    Yamaoka, Masanao
    [J]. 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2021, 64 : 64 - +
  • [4] Scaling out Ising machines using a multi-chip architecture for simulated bifurcation
    Tatsumura, Kosuke
    Yamasaki, Masaya
    Goto, Hayato
    [J]. NATURE ELECTRONICS, 2021, 4 (03) : 208 - 217
  • [5] Yamamoto K., 2022, P IEEE 20 JUB WORLD, P225, DOI [10.1109/SAMI54271.2022.9780844, DOI 10.1109/SAMI54271.2022.9780844]
  • [6] Yamamoto K., "IEEE J. Solid -State Circuits
  • [7] Scalable fully coupled annealing processing system and multi-chip FPGA implementation
    Yamamoto, Kaoru
    Kawahara, Takayuki
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2022, 95
  • [8] A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems
    Yamamoto, Kasho
    Takemoto, Takashi
    Yoshimura, Chihiro
    Mashimo, Mayumi
    Yamaoka, Masanao
    [J]. IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021), 2021,