Design and implementation of dual-mode configurable memory architecture for CNN accelerator

被引:0
|
作者
Shan, Rui [1 ]
Li, Xiaoshuo [1 ]
Gao, Xu [1 ]
Huo, Ziqing [1 ]
机构
[1] School of Electronic Engineering, Xián University of Posts and Telecommunications, Xi’an,710121, China
关键词
Architecture - Integrated circuit design - Memory management units - Parallel architectures - Particle accelerators - Reconfigurable architectures - Reconfigurable hardware;
D O I
10.3772/j.issn.1006-6748.2024.02.012
中图分类号
学科分类号
摘要
With the rapid development of deep learning algorithms, the computational complexity and functional diversity are increasing rapidly. However, the gap between high computational density and insufficient memory bandwidth under the traditional von Neumann architecture is getting worse. Analyzing the algorithmic characteristics of convolutional neural network (CNN), it is found that the access characteristics of convolution (CONV) and fully connected (FC) operations are very different. Based on this feature, a dual-mode reconfigurable distributed memory architecture for CNN accelerator is designed. It can be configured in Bank mode or first input first output (FIFO) mode to accommodate the access needs of different operations. At the same time, a programmable memory control unit is designed, which can effectively control the dual-mode configurable distributed memory architecture by using customized special accessing instructions and reduce the data accessing delay. The proposed architecture is verified and tested by parallel implementation of some CNN algorithms. The experimental results show that the peak bandwidth can reach 13. 44 GB·s - 1 at an operating frequency of 120 MHz. This work can achieve 1. 40, 1. 12, 2. 80 and 4. 70 times the peak bandwidth compared with the existing work. © 2024 Inst. of Scientific and Technical Information of China. All rights reserved.
引用
收藏
页码:211 / 220
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