Implementation of Polyphase Digital Down Converter Using Optimized LMS Algorithm for WCDMA Application

被引：0

作者：

Datta, Debarshi ^{[1
]}

Naskar, Mrinal Kanti ^{[1
]}

机构：

[1] Jadavpur Univ, Dept ETCE, Kolkata 700032, India

来源：

IEEE EMBEDDED SYSTEMS LETTERS | 2024年 / 16卷 / 04期

关键词：

Field programmable gate arrays; Convergence; Adaptive filters; Filtering; Dynamic range; Spread spectrum communication; Particle swarm optimization; Multiaccess communication; Hardware; Computer architecture; Digital down converter (DDC); field-programmable gate array (FPGA); least mean square (LMS); particle swarm optimization (PSO); spurious-free dynamic range (SFDR); DESIGN;

D O I：

10.1109/LES.2024.3473539

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This letter presents the implementation of a polyphase digital down converter (DDC) that employs a least mean square (LMS) algorithm associated with particle swarm optimization (PSO) for the wideband code division multiple access (WCDMA) application. The PSO-based LMS algorithm suppresses the noise signal, enabling a significant improvement in the spurious-free dynamic range (SFDR), which is 130 dB. The complex multiplication is realized by the canonical impel-mentation to reduce the number of multipliers. The suggested polyphase DDC architecture is successfully implemented in the field-programmable gate array device (FPGA) Kintex-7 platform. To achieve high accuracy, the proposed design is implemented with an efficient user-defined floating-point representation data type. Synthesis results suggested that the design consumes less area and power compared to the most recent structure.

引用

页码：533 / 536

页数：4

共 13 条

[1] A Pipelined Reduced Complexity Two-Stages Parallel LMS Structure for Adaptive Beamforming [J].