Modeling and Evaluation Framework for Constrained Dataflow in Spatial Accelerators

被引:0
作者
He, Yuxing [1 ,2 ]
Wang, Teng [2 ]
Teng, Wenbin [1 ,2 ]
Gong, Lei [1 ,2 ]
机构
[1] School of Computer Science and Technology, University of Science and Technology of China, Hefei,230027, China
[2] Suzhou Institution for Advanced Research, University of Science and Technology of China, Jiangsu, Suzhou,215123, China
关键词
Structural analysis;
D O I
10.3778/j.issn.1002-8331.2311-0443
中图分类号
学科分类号
摘要
Deploying tensor computation tasks on spatial accelerators has been proven to effectively improve the execution speed and efficiency of tensor computations. To effectively deploy tensor computation on spatial accelerators, various dataflow modeling and evaluation frameworks have been proposed in academia. These frameworks enable quick evaluation of dataflows for efficient design space exploration. However, these frameworks lack fine-grained descriptions of the hardware structure, making it challenging to effectively model the constraints imposed by the hardware structure on the dataflow. As a result, they fail to explore the design space of dataflows constrained by real spatial accelerators effectively. To address this issue, this paper firstly provides a fine-grained modeling of the hardware architecture, using a multi-level spatial accelerator hardware structure as a template. Each level consists of three components: array structure, storage structure, and interconnect network structure, to respectively describe the constraints of the hardware architecture on spatial unfolding of data flow, storage capacity, and data transmission methods. Then, this paper proposes a tensor computation task and dataflow modeling approach that can solve the resource requirements of the dataflow. Based on this, the paper further proposes a dataflow evaluation framework, consisting of three parts: requirement analysis, constraint analysis, and performance analysis. The requirement analysis is used to determine the demands of computation tasks and dataflows on hardware resources. The constraint analysis aims to examine whether the dataflow violates hardware structure constraints. The performance analysis is used to evaluate performance metrics such as latency, data reuse, and resource utilization of the dataflow. Experimental results demonstrate that compared to the state-of-the-art evaluation framework, the proposed framework reduces the error in latency evaluation, and effectively supports the exploration of constrained dataflow design space. © 2024 Journal of Computer Engineering and Applications Beijing Co., Ltd.; Science Press. All rights reserved.
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页码:74 / 88
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