An architecture for high performance control using digital signal processor chips

A computing structure for control applications in which there is a natural hierarchical structure (allowing algorithms devoted to simple tasks to be placed at the lowest level and complex tasks at the higher levels) is described. The architecture consists of a high-level general-purpose computer (host) and up to eight digital signal processors (DSPs) that can be interfaced with the controlled plant(s). The high-level computer is either a work station or an advanced personal computer with sufficient memory space (RAM and mass memory), equipped with peripherals for implementation of user-friendly interface, and with the ability to communicate with other computers, perhaps in a local network. The synchronization and the real-time communications between the host and a DSP are implemented by the two memory banks alternatively switched between the host and the DSP. A complete transparency and a minimum overhead result for the tasks running on the DSP.