共 50 条
[1]
A new ATM switch architecture: Scalable shared buffer
[J].
ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2,
1996,
:772-775
[2]
Architecture, defect tolerance, and buffer design for a new ATM switch
[J].
SECOND ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1997 PROCEEDINGS,
1997,
:248-258
[3]
Architecture, defect tolerance, and buffer design for a new ATM switch
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING,
1998, 21 (04)
:338-345
[4]
A modular and scalable ATM switch using shared buffer architecture
[J].
APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96,
1996,
:318-321
[6]
A CAM-based VLSI architecture for shared buffer ATM switch with fuzzy controlled buffer management
[J].
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS,
1996,
:149-152
[8]
A multicasting ATM switch architecture
[J].
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE,
1997,
:2140-2143
[9]
An output-shared buffer ATM switch
[J].
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS,
1996,
:147-148
[10]
Adaptive buffer threshold updating for an ATM switch
[J].
THIRD IEEE SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS, PROCEEDINGS,
1998,
:400-405