Low power monolithic subsampled phase-locked loop architecture for wireless transceivers

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作者：

Univ of Waterloo, Waterloo, Canada ^{[1
]}

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来源：

Proc IEEE Int Symp Circuits Syst | / II-549 - II-552期

关键词：

Phase detector - Phase noise - Wireless transceivers;

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摘要：

A subsampling stage driven by a crystal reference eliminates the prescaler and greatly reduces the division ratio of the PLL. The wide bandwidth of the loop inhibits the VCO phase-noise, allowing for the use of on-chip VCOs. The resulting architecture is particularly suitable for DDS-driven PLL architectures since it relaxes the requirements on the DDS thus further reducing the power consumption. The advantages of the architecture are highlighted and system- and circuit-level simulations are presented.

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