A system for efficiently self-reconstructing 1 1/2-track switch torus arrays

被引：0

作者：

Horita, T. ^{[1
]}

Takanami, I. ^{[1
]}

机构：

[1] Dept. of Information and Comp. Sci., Polytechnic University, Sagamihara-shi, 229-1196, Japan

来源：

IEICE Transactions on Information and Systems | 2001年 / E84-D卷 / 12期

关键词：

Algorithms - Computer simulation - Multiplexing equipment - Parallel processing systems - Response time (computer systems) - Switching circuits - WSI circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we introduce the 1 1/2-track switch torus array by changing the connections in 1 1/2-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 1 1/2-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method, hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.

引用

页码：1801 / 1809