FLOW OF INSTRUCTIONS THROUGH A PIPELINED PROCESSOR.

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Wood, W.F.
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723 Computer Software; Data Handling and Applications;
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The paper describes the treatment of pipelined processors by both analytic and discrete-event simulation models and emphasizes the importance of analytical models in decision making. The results obtained show that intrinsic delays in a pipeline may easily be erroneously attributed to extraneous factors such as store-accessing delays or jumps in instruction sequences.
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页码:59 / 78
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