Low power full-search block-matching motion estimation chip for H.263+

被引:0
作者
Shen, Jun-Fu [1 ]
Chen, Liang-Gee [1 ]
Chang, Hao-Chieh [1 ]
Wang, Tu-Chih [1 ]
机构
[1] Natl Taiwan Univ, Taipei, Taiwan
来源
Proceedings - IEEE International Symposium on Circuits and Systems | 1999年 / 4卷
关键词
Bit error rate - CMOS integrated circuits - Electric network synthesis - Energy utilization - Image coding - Image quality - Pattern matching - Precision engineering - Real time systems - VLSI circuits;
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摘要
In this paper, a low power full-search block matching (FSBM) motion estimation design for the H.263+ low bit rate video coding was proposed. The features of H.263+ such as half-pixel precision and some advanced modes (advance prediction mode, PB-frame mode and reduced resolution update mode) are taken into consideration. This architecture can deal with different block size and searching range in a single chip without any latency. We use a 1-D and 2-D mixed architecture to fulfill this goal. To achieve the purpose of low power and reduce the design period, we use dual supply voltage levels in this chip. This chip is realized by TSMC 0.6 um single-poly triple-metal CMOS technology. The operation frequency is set at 60 MHz to meet the requirement of the real time processing in the reduced resolution update mode in H.263+. The power consumption is 424 mW at 60 MHz and the throughput is 36 frames per second with CIF format at 60 MHz.
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