Si-SiO2 electronic interface roughness as a consequence of Si-SiO2 topographic interface roughness

Numerical calculations were used to assess the probable microscopic distribution of the electric field along or close to the actual Si-SiO2 interface of a metal oxide semiconductor (MOS) capacitor biased into accumulation. Silicon wafers were oxidized to 20 nm at 1150°C by rapid thermal oxidation, according to two different thermal recipes in order to yield different Si-SiO2 interface roughnesses. After oxide removal, typical atomic force microscopy (AFM) line scans of the silicon surface were exported into the MEDICI program as a description of the Si-SiO2 interface in order to calculate the electric field distribution within the oxide layer of a bidimensional MOS capacitor biased into accumulation. This distribution was found to be highly inhomogeneous even for relatively smooth Si-SiO2 interfaces, displaying strong local electric field enhancements, the spatial distribution of which will be called electronic roughness in this work. Simple local oxide thinning at the position of the protrusions cannot account for these field enhancements, thus indicating that the shape of the protrusion is dictating the electronic roughness. The electronic roughness could be correlated with electric breakdown characteristics of actual MOS capacitors prepared on these wafers.