On efficiency of transport triggered architectures in DSP applications

被引：0
|
作者：
Heikkinen, Jari [1 ]
Takala, Jarmo [1 ]
Cilio, Andrea [2 ]
Corporaal, Henk [3 ]
机构：
[1] Tampere University of Technology, P.O.B. 553, 33101 Tampere, Finland
[2] Delft University of Technology, Mekelweg 4, 2628 CD Delft, Netherlands
[3] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
来源：
Advances in Systems Engineering, Signal Processing and Communications | 2002年
关键词：
Benchmarking - Computer aided software engineering - Computer architecture - Data transfer - Encoding (symbols) - Fast Fourier transforms - High level languages - Parallel processing systems - Program compilers;
D O I：
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学科分类号：
摘要：
The trend in programmable architectures for digital signal processing (DSP) is to move towards high-level language programming, which sets high requirements for compilers to efficiently exploit the instruction level parallelism in modern processors. In this paper, efficiency of transport triggered architectures (TTA) in DSP applications is discussed. The efficiency of a high-level compiler on a TTA is compared to commercial very long instruction word DSP architecture. The effect of different coding styles in high-level language code is evaluated with a DSP benchmark, fast Fourier transform.
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页码：25 / 29
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