ACL. . . ADVANCED CMOS LOGIC THAT LENGTHENS THE STRIDE OF LOW-POWER SYSTEMS.

被引:0
|
作者
Croes, R.
de Pagter, A.
机构
来源
关键词
CMOS LOGIC - HIGH RELIABILITY - LOW-POWER SYSTEMS - NOISE MARGINS - REDUCED POWER DISSIPATION;
D O I
暂无
中图分类号
学科分类号
摘要
(Edited Abstract)
引用
收藏
页码:66 / 75
相关论文
共 50 条
  • [41] LOW-POWER DYNAMIC TERNARY LOGIC
    WANG, JS
    WU, CY
    TSAI, MK
    IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1988, 135 (06): : 221 - 230
  • [42] Logic transformation for low-power synthesis
    Kim, KW
    Kim, T
    Hwang, TT
    Kang, SM
    Liu, CL
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2002, 7 (02) : 265 - 283
  • [43] Advanced CMOS technologies for ultra-low power logic and AI applications
    Takagi, Shinichi
    Toprasertpong, Kasidit
    Kato, Kimihiko
    Sumita, Kei
    Nako, Eishin
    Nakane, Ryosho
    Jo, Kwang-won
    Takenaka, Mitsuru
    2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM), 2021,
  • [44] Low power CMOS logic families
    Allam, MW
    Elmasry, MI
    1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, 1999, : 419 - 422
  • [45] Adiabatic Capacitive Logic: a paradigm for low-power logic
    Pillonnet, G.
    Fanet, H.
    Houri, S.
    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 2767 - 2770
  • [46] A low-power CMOS mixer for low-IF receivers
    Zencir, E
    Dogan, NS
    Arvas, E
    RAWCON 2002: IEEE RADIO AND WIRELESS CONFERENCE, PROCEEDINGS, 2002, : 157 - 160
  • [47] Low-Voltage Low-Power CMOS Design
    Dokic, Branko L.
    Pesic-Brdanin, Tatjana
    Cavka, Drago
    2016 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (INDEL), 2016,
  • [48] A low input, low-power dissipation CMOS ADC
    Wang, Biye
    He, Lili
    Jones, Morris
    ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 383 - +
  • [49] Complete delay modeling of sub-threshold CMOS logic gates for low-power application
    Chanda, Manash
    Chakraborty, Ananda Sankar
    Sarkar, Chandan Kumar
    INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2016, 29 (02) : 132 - 145
  • [50] DEPLETION ENHANCEMENT CMOS FOR A LOW-POWER FAMILY OF 3-VALUED LOGIC-CIRCUITS
    HEUNG, A
    MOUFTAH, HT
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (02) : 609 - 616