Fast timing simulation of transient faults in digital circuits

被引：0

作者：

Dharchoudhury, A. ^{[1
]}

Kang, S.M. ^{[1
]}

Cha, H. ^{[1
]}

Patel, J.H. ^{[1
]}

机构：

[1] Univ of Illinois at Urbana-Champaign, Urbana, United States

来源：

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1994年

关键词：

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

页码：719 / 722

共 50 条

[1] SIMULATION AND ANALYSIS OF TRANSIENT FAULTS IN DIGITAL CIRCUITS
YANG, FL
SALEH, RA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (03) : 258 - 264
[2] A FAST TIMING SIMULATOR FOR MOS DIGITAL CIRCUITS
ZOU, F
AEU-ARCHIV FUR ELEKTRONIK UND UBERTRAGUNGSTECHNIK-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 1990, 44 (02): : 148 - 152
[3] A FAST-TIMING SIMULATOR FOR DIGITAL MOS CIRCUITS
TSAO, D
CHEN, CF
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1986, 5 (04) : 536 - 540
[4] A method for fast simulation of multiple catastrophic faults in analogue circuits
Tadeusiewicz, Michal
Halgas, Stanislaw
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2010, 38 (03) : 275 - 290
[5] HARDWARE ACCELERATORS FOR TIMING SIMULATION OF VLSI DIGITAL CIRCUITS
LEWIS, DM
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (11) : 1134 - 1149
[6] Timing simulation of digital circuits with binary decision diagrams
Ubar, R
Jutman, A
Peng, Z
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 460 - 466
[7] ILLIADS - A FAST TIMING AND RELIABILITY SIMULATOR FOR DIGITAL MOS CIRCUITS
SHIH, YH
LEBLEBICI, Y
KANG, SM
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (09) : 1387 - 1402
[8] A technique for fast transient statistical simulation of analog circuits
López-Ahumada, R
Rodríguez-Macías, R
42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1999, : 64 - 67
[9] LOCALIZATION OF FAULTS IN DIGITAL CIRCUITS
GROBMAN, DM
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1983, (02): : 79 - 84
[10] Simulation of transient processes in the fast track-and-hold circuits
Jasonis, V.
Maircinkevicius, A. J.
ELEKTRONIKA IR ELEKTROTECHNIKA, 2008, (03) : 59 - 62

← 1 2 3 4 5 →