Low-power switched-current algorithmic A/D converter

被引：0
|
作者：
Tezel, A. [1 ]
Akin, T. [1 ]
机构：
[1] Middle East Technical Univ, Ankara, Turkey
来源：
Proceedings - IEEE International Symposium on Circuits and Systems | 1999年 / 1卷
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [31] Low-power high-frequency class-AB two-step sampling switched-current techniques
    Worapishet, A
    Hughes, JB
    Toumazou, C
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2003, 50 (09) : 649 - 653
  • [32] A low-power 7-b 33-Msamples/s switched-current pipelined ADC for motor control
    Sung, Guo-Ming
    Tzeng, Jyi-Hrong
    Liao, Chen-Shen
    Shu, Shih-Chieh
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 171 - +
  • [33] Low power switched-current circuits with low sensitivity to the rise/fall time of the clock
    Rudnicki, Radek
    Kropidlowski, Marek
    Handkiewicz, Andrzej
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2010, 38 (05) : 471 - 486
  • [34] Low voltage BICMOS switched-current circuits
    Hamed, HFA
    Khalil, AH
    Embabi, SHK
    Salama, AE
    ICM'99: ELEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, 1999, : 205 - 208
  • [35] NEED A LOW-POWER D-A CONVERTER
    ESTEP, GJ
    ELECTRONIC PRODUCTS MAGAZINE, 1979, 22 (03): : 47 - 49
  • [36] A low-power inverted ladder D/A converter
    Perelman, Yevgeny
    Ginosar, Ran
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (06) : 497 - 501
  • [37] A low-power low-mismatch low-glitch class AB first-generation switched-current memory cell and its applications
    San-Um, W
    Srisuchinwong, B
    Tantaratana, S
    TENCON 2004 - 2004 IEEE REGION 10 CONFERENCE, VOLS A-D, PROCEEDINGS: ANALOG AND DIGITAL TECHNIQUES IN ELECTRICAL ENGINEERING, 2004, : D258 - D261
  • [38] 3 V, 10 bit, 6.4 MHz switched-current CMOS A/D converter design
    Generic Radio Network Products, Stockholm, Sweden
    Proc IEEE Int Conf Electron Circuits Syst, (27-30):
  • [39] A low-power switched-current CDMA matched filter with on-chip V-I and I-V converters
    Yamasaki, T
    Nakayama, T
    Shibata, T
    2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 214 - 217
  • [40] Design and implementation of an algorithmic S2I switched-current multiplier
    Manganaro, G
    de Gyvez, JP
    ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : 37 - 40
12345