TRENDS IN HIGH DENSITY PACKAGING OF I/O CHIP CARRIERS.

被引：0

作者：

Geschwind, Gary ^{[1
]}

Snyder, Dan ^{[1
]}

机构：

[1] Raychem Corp, Menlo Park, CA, USA, Raychem Corp, Menlo Park, CA, USA

来源：

Electri-onics | 1985年 / 31卷 / 09期

关键词：

INTEGRATED CIRCUITS; VLSI;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Conventional 100-mil center dual in-line packages (DIP) are not suitable for new generation integrated circuits because they take up too much board area and compromise electrical performance. This is because the long and asymmetric I/O paths cause timing and impedance problems with the fast rise and cycle times of these devices. The new packages which have been proposed as solutions during recent years overcame some of the objections to the DIP. However, no clear solution has emerged because each has shown difficulty because of carrier-to-substrate assembly, test, inspection, and reliability problems at the second level of interconnect. These packages include leadless chip carriers (LCC), fine-pitch leaded packages, pin grid array packages (PGAP's), pad array packages, and plastic leaded chip carriers (PLCC). This article focuses on problems in assembling these new packages in surface mount and through-hole applications, as well as some new alternatives available to packaging engineers.

引用

页码：39 / 42