LOGIC DELAY CHARACTERIZATION OF A LSSD LOGIC CIRCUIT USING A SCAN RING.

This article describes the use of a scan ring in a level sensitive scan design (LSSD) logic circuit to measure logic delay characteristics. Software programs can simulate logic delay characteristics, but do not use real hardware to verify the delays. Further methods of measuring logic delay include varying oscillator speed, but in many systems the oscillator cannot be varied. The method described does not require any additional hardware and uses existing logic in the scan ring.