RISC IMPLEMENTATION ON CHIP AND BOARD.

To challenge large computers successfully in computer-intensive applications, microprocessor-based systems designers require microprocessors capable of delivering levels of performance rivalling superminicomputers and mainframes. Combined with an efficient memory hierarchy in a multiple-bus architecture, a recently announced RISC CPU and supporting coprocessors work closely with optimizing compilers to execute five million instructions per second (mips) in a single-board processor subsystem. By exploiting the ability of RISC-based design to provide both high-performance and extensive functional capability, designers can create systems able to serve applications once reserved for much larger machines.