共 50 条
- [1] Massively parallel VLSI architecture for a multilayered neural network Systems and Computers in Japan, 1993, 24 (12): : 78 - 87
- [2] ARCHITECTURE AND APPLICATIONS OF A HETEROGENEOUS, MASSIVELY PARALLEL MACHINE ANNUAL REVIEW OF COMPUTER SCIENCE, 1986, 1 : 139 - 151
- [5] Analysis of topologies of massively parallel processing architecture Dianzi Keji Daxue Xuebao/Journal of University of Electronic Science and Technology of China, 1994, 23 (06):
- [6] A RISC CENTRAL PROCESSING UNIT FOR A MASSIVELY PARALLEL ARCHITECTURE MICROPROCESSING AND MICROPROGRAMMING, 1990, 30 (1-5): : 33 - 39
- [7] Massively scalable prototype learning for heterogeneous parallel computing architecture Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology, 2016, 48 (11): : 53 - 60
- [8] Implementation approach of the IEEE 1149.1 for the routing test of a VLSI massively parallel architecture Journal of Electronic Testing: Theory and Applications (JETTA), 1998, 12 (03): : 171 - 185
- [9] An implementation approach of the IEEE 1149.1 for the routing test of a VLSI massively parallel architecture JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 12 (03): : 171 - 185
- [10] An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture Journal of Electronic Testing, 1998, 12 : 171 - 185