VLSI ARCHITECTURES FOR COMPUTING MULTIPLICATIONS AND INVERSES IN GF(2M).

被引：223

作者：

Wang, Charles C. ^{[1
]}

Truong, T.K. ^{[1
]}

Shao, Howard M. ^{[1
]}

Deutsch, Leslie J. ^{[1
]}

Omura, Jim K. ^{[1
]}

Reed, Irving S. ^{[1
]}

机构：

[1] JPL, Pasadena, CA, USA, JPL, Pasadena, CA, USA

来源：

IEEE Transactions on Computers | 1985年 / C-34卷 / 08期

关键词：

CODES; SYMBOLIC; -; Encoding; COMPUTERS; MICROCOMPUTER - Multiplying Circuits - CRYPTOGRAPHY;

D O I：

10.1109/TC.1985.1676616

中图分类号：

学科分类号：

摘要：

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. J. L. Massey and J. K. Omura recently (1981) developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2**m ). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2**m ). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and, therefore, naturally suitable for VLSI implementation. 12 refs.

引用

页码：709 / 717