OFFSET WORD-LINE ARCHITECTURE FOR SCALING DRAM'S TO THE GIGABIT LEVEL.

被引：0

作者：

Scheuerlein, Roy E. ^{[1
]}

Meindl, James D. ^{[1
]}

机构：

[1] Stanford Univ, CA, USA, Stanford Univ, CA, USA

来源：

IEEE Journal of Solid-State Circuits | 1987年 / 23卷 / 01期

关键词：

COMPUTER ARCHITECTURE - Design - DATA STORAGE; SEMICONDUCTOR - Fabrication - SEMICONDUCTOR DEVICES; MOS;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

An alternative to the boosted word-line DRAM architecture is described that is scalable to the gigabit level and avoids the problems of poor performance and high gate fields of conventional boosted word-line circuits. The alternative is called an offset word-line architecture, because the cell switch is changed to depletion mode and the word line is pulled beyond the cell switch device's source voltage rather than boosted beyond its drain voltage. The large voltage swing for the word line does not cause large fields across the gate dielectric in the word-line driver or array access device because the gates of some devices use materials with modified work functions. The word-line voltage swing can be greater than the bit-line voltage swing plus the required threshold voltage even for gigabit-scale integration DRAM technologies.

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