Design guidelines for SOI gate controlled hybrid transistor operating at low voltage

The comprehensive design guidelines are provided in this paper for the first time, especially for GCHT operating at low voltage, which is an advantageous operating region of GCHT. The examined mechanisms in this study involve in the short channel effect, current driving capability, device off-characteristic and open-circuit voltage gain, with both digital applications and analog applications requirement considered. Five key parameters are taken into account, including the channel length (base width), gate oxide thickness, channel doping concentration, silicon film thickness and the buried oxide thickness. Considering the design criteria for low voltage, the above-mentioned different mechanisms are investigated. The design curves for low operating voltage (0.8 V) are presented by synthesizing the results. The tradeoffs between different parameter requirements for different effects are explicitly illuminated in the design figure, showing the greatly-extend allowable design region and pointing out the direction for the deep submicron device development. The data disposal method presented in this paper can be used to the practical device and circuit design with a reliable processing line.