Interconnect coupling noise in CMOS VLSI circuits

被引:0
|
作者
Tang, Kevin T. [1 ]
Friedman, Eby G. [1 ]
机构
[1] Univ of Rochester, Rochester, NY, United States
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:48 / 53
相关论文
共 50 条
  • [11] Reduction of crosstalk noise between interconnect lines in CMOS RF integrated circuits
    Ootera, H
    Nishikawa, K
    Yamakawa, S
    Oomori, T
    Tanabe, S
    2002 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1 AND 2, SYMPOSIUM RECORD, 2002, : 866 - 870
  • [12] INTERCONNECT MATERIALS FOR VLSI CIRCUITS .3. MATERIALS FOR INTERCONNECT LINES
    PAULEAU, Y
    SOLID STATE TECHNOLOGY, 1987, 30 (06) : 101 - 105
  • [13] FAULT SIMULATION IN CMOS VLSI CIRCUITS
    ZAGHLOUL, ME
    GOBOVIC, D
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1991, 138 (04): : 203 - 212
  • [14] EFFICIENT TESTS FOR CMOS VLSI CIRCUITS
    RADHAKRISHNAN, D
    LAI, CM
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1991, 71 (01) : 29 - 43
  • [15] Effect of inductance on interconnect propagation delay in VLSI circuits
    Ligocka, A
    Bandurski, W
    SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS, 2004, : 121 - 124
  • [16] Modeling and extraction of interconnect capacitances for multilayer VLSI circuits
    Arora, ND
    Raol, KV
    Schumann, R
    Richardson, LM
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (01) : 58 - 67
  • [17] Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits
    Heydari, P
    Pedram, M
    2001 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD 2001, PROCEEDINGS, 2001, : 104 - 109
  • [18] Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits
    Bai, XL
    Chandra, R
    Dey, S
    Srinivas, PV
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (08) : 1256 - 1263
  • [19] Delay analysis of UDSM CMOS VLSI circuits
    Samanta, Jagannath
    De, Bishnu Prasad
    INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011, 2012, 30 : 135 - 143
  • [20] A design reliability methodology for CMOS VLSI circuits
    Oshiro, L
    Radojcic, R
    1995 INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT, 1996, : 34 - 39