SOI implementation of a 64-bit adder

被引：0
|
作者：
Tran, J.V. [1 ]
Mounes-Toussi, F. [1 ]
Storino, S.N. [1 ]
Stasiak, D.L. [1 ]
机构：
[1] IBM Corp, Rochester, United States
来源：
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 1999年
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：573 / 574
相关论文
共 50 条
  • [1] Implementation of a 64-bit Jackson Adder
    McAuley, Tynan
    Koven, William
    Carter, Andrew
    Ning, Paula
    Harris, David Money
    2013 ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, 2013, : 1149 - 1154
  • [2] Implementation of an efficient 64-bit Carry Select Adder using Muxes
    Chandran, Rahul G.
    Saraswathi, N.
    2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 430 - 434
  • [3] SOI-optimized 64-bit high-speed CMOS adder design
    Kim, JJ
    Joshi, R
    Chuang, CT
    Roy, K
    2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2002, : 122 - 125
  • [4] A 64-bit decimal floating-point adder
    Thompson, J
    Karra, N
    Schulte, MJ
    VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 297 - 298
  • [5] Implementation of 64-Bit Kogge Stone Carry Select Adder with ZFC for Efficient Area
    Tapasvi, B.
    Sinduri, K. Bala
    Lakshmi, B. G. S. S. B.
    Kumar, N. Udaya
    2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES, 2015,
  • [6] Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
    IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, United States
    不详
    IEEE J Solid State Circuits, 8 (1108-1117):
  • [7] Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
    Hwang, W
    Gristede, GD
    Sanda, P
    Wang, SY
    Heidel, DF
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (08) : 1108 - 1117
  • [8] Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability
    Hwang, W
    Gristede, GD
    Sanda, PN
    Wang, SY
    Heidel, DF
    IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 519 - 522
  • [9] 480ps 64-bit Race Logic adder
    Lee, SJ
    Woo, R
    Yoo, HJ
    2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2001, : 27 - 28
  • [10] A 64-bit fast adder with 0.18μm CMOS technology
    Jin, ZP
    Shen, XB
    Bai, YQ
    International Symposium on Communications and Information Technologies 2005, Vols 1 and 2, Proceedings, 2005, : 1167 - 1171
12345