FPGA-based hash circuit synthesis with evolutionary algorithms

被引:0
作者
Damiani, Ernesto [1 ]
Liberali, Valentino [2 ]
Tettamanzi, Andrea G. B. [1 ]
机构
[1] Polo Didattico e di Ricerca di Crema, University of Milan
[2] Department of Electronics, University of Pavia
来源
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 1999年 / E83-A卷 / 09期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:1888 / 1896
相关论文
共 50 条
[41]   A FPGA-based processing Circuit Design and Realization for Baseband signals of RFID [J].
Ren, Wenping ;
Shao, Chunlin ;
Miao, Aimin ;
He, Jiqin .
2016 IEEE INTERNATIONAL CONFERENCE OF ONLINE ANALYSIS AND COMPUTING SCIENCE (ICOACS), 2016, :330-333
[42]   A Multi-Faceted Approach to FPGA-Based Trojan Circuit Detection [J].
Patterson, Michael ;
Mills, Aaron ;
Scheel, Ryan ;
Tillman, Julie ;
Dye, Evan ;
Zambreno, Joseph .
2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,
[43]   PNoC: a flexible circuit-switched NoC for FPGA-based systems [J].
Hilton, C. ;
Nelson, B. .
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2006, 153 (03) :181-188
[44]   AUTOMATED SYNTHESIS OF FPGA-BASED HETEROGENEOUS INTERCONNECT TOPOLOGIES [J].
Cilardo, Alessandro ;
Fusella, Edoardo ;
Gallo, Luca ;
Mazzeo, Antonino .
2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS, 2013,
[45]   Architectures and Algorithms for Image and Video Processing using FPGA-based Platform [J].
Pandey, J. G. ;
Karmakar, A. ;
Shekhar, C. ;
Gurunarayanan, S. .
18TH INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AND TEST, 2014,
[46]   Plaster: an Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms [J].
Farinelli, Lorenzo ;
De Vincenti, Daniele Valentino ;
Damiani, Andrea ;
Stornaiuolo, Luca ;
Brondolin, Rolando ;
Santambrogio, Marco D. ;
Sciuto, Donatella .
2021 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 2021, :104-107
[47]   A Scalable FPGA-based Accelerator for High-Throughput MCMC Algorithms [J].
Hosseini, Morteza ;
Islam, Rashidul ;
Kulkarni, Amey ;
Mohsenin, Tinoosh .
2017 IEEE 25TH ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2017), 2017, :201-201
[48]   FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256 [J].
Algredo-Badillo, I. ;
Feregrino-Uribe, C. ;
Cumplido, R. ;
Morales-Sandoval, M. .
MICROPROCESSORS AND MICROSYSTEMS, 2013, 37 (6-7) :750-757
[49]   FPGA-based Controllers [J].
Monmasson, Eric ;
Idkhajine, Lahoucine ;
Naouar, Mohamed Wissem .
IEEE INDUSTRIAL ELECTRONICS MAGAZINE, 2011, 5 (01) :14-26
[50]   Secure Hash Algorithms and the Corresponding FPGA Optimization Techniques [J].
Al-Odat, Zeyad A. ;
Ali, Mazhar ;
Abbas, Assad ;
Khan, Samee U. .
ACM COMPUTING SURVEYS, 2020, 53 (05)