PHASE-FOLLOWING DIGITAL FREQUENCY-LOCKED LOOP SYSTEM.

被引:0
|
作者
Yuge, Tetsuya
Ozawa, Shinji
Mori, Shinsaku
机构
来源
| 1600年 / 59期
关键词
Compendex;
D O I
暂无
中图分类号
学科分类号
摘要
PHASE LOCKED LOOPS
引用
收藏
相关论文
共 50 条
  • [1] PHASE-FOLLOWING DIGITAL FREQUENCY-LOCKED LOOP SYSTEM
    YUGE, T
    OZAWA, S
    MORI, S
    ELECTRONICS & COMMUNICATIONS IN JAPAN, 1976, 59 (04): : 42 - 51
  • [2] A Digital Frequency-Locked Loop System for Capacitance Measurement
    Dean, Robert Neal
    Rane, Aditi Kiran
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2013, 62 (04) : 777 - 784
  • [3] 50-MHZ PHASE-LOCKED AND FREQUENCY-LOCKED LOOP
    CORDELL, RR
    FORNEY, JB
    DUNN, CN
    GARRETT, WG
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (06) : 1003 - 1010
  • [4] Convergence and output MSE of digital frequency-locked loop for wireless communications
    Ling, FY
    1996 IEEE 46TH VEHICULAR TECHNOLOGY CONFERENCE, PROCEEDINGS, VOLS 1-3: MOBILE TECHNOLOGY FOR THE HUMAN RACE, 1996, : 1215 - 1219
  • [5] A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop
    Hong, Yu-Meng
    Lin, Tsung-Hsien
    2023 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI-TSA/VLSI-DAT, 2023,
  • [6] A study of nonlinearities for a frequency-locked loop principle
    Albrecht, S
    Gothenberg, A
    Sumi, Y
    Tenhunen, H
    2003 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, 2003, : 71 - 75
  • [7] A Novel Three-Phase Software Phase-Locked Loop Based on Frequency-Locked Loop and Initial Phase Angle Detection Phase-Locked Loop
    Wang, Liang
    Jiang, Qirong
    Hong, Lucheng
    38TH ANNUAL CONFERENCE ON IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2012), 2012, : 150 - 155
  • [8] A Sub-Sampling Phase-Locked Loop With a Robust Agile-Locking Frequency-Locked Loop
    Chen, Chia-Min
    Hong, Yu-Meng
    Lin, Tsung-Hsien
    2023 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI-TSA/VLSI-DAT, 2023,
  • [9] Winner-Take-All Neural Network with Digital Frequency-Locked Loop
    Hikawa, Hiroomi
    2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 2517 - 2520
  • [10] STEADY STATES OF AN ANALOG-DIGITAL PHASE-LOCKED LOOP SYSTEM.
    Karyakin, V.L.
    Telecommunications and Radio Engineering (English translation of Elektrosvyaz and Radiotekhnika), 1981, 35-36 (02): : 70 - 72