Realization of pipelined multiplier-free FIR digital filter

被引：0
|
作者：
Dawoud, D.S. [1 ]
机构：
[1] Univ of Botswana, Gaborone, Botswana
来源：
IEEE AFRICON Conference | 1999年 / 1卷
关键词：
Algorithms - Frequency multiplying circuits - Signal encoding - Time varying control systems;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The paper introduces a high-speed multiplication-free realization for FIR filter. The realization is based on the use of a linear periodically time-varying (PTV) system and the use of radix- r recoding schemes for obtaining the filter coefficients. The paper combined and reformulated the Modified Booth multiplication algorithm and the filter operation in bit-level. As a result, two schemes are proposed. The structures can be used to build programmable FIR filter.
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收藏
页码：335 / 338
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