Switching current and noise reduction by clock distribution

被引：0

作者：

Raič, Dušan ^{[1
]}

机构：

[1] Univerza v Ljubljani, Fakulteta za Elektrotehniko, Tržaška 25, 1000 Ljubljana, Slovenia

来源：

Elektrotehniski Vestnik/Electrotechnical Review | 2000年 / 67卷 / 02期

关键词：

Noise abatement - Timing circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Distributed clocking violates the basic principle of synchronous logic, relying on one central clock. To compensate for the delays in the distributed signals, the reverse clocking principle was used. This technique has been reported mainly to prevent pipeline malfunctions at high speeds when clock lines start to exhibit RC line effects.

引用

页码：111 / 116