Performance and design of CMOS-DRAM

The design methodology and the performance advantages of a CMOS-DRAM recently developed are discussed. Arranging the cell array in a N-well decreases the soft error rate. By means of CMOS circuits, the peripheral circuit is made static, the whole circuit is simplified, and the speed and reliability are increased. The key circuits, such as S/R amplifier, clock generator, row decoder and redundant circuits are analzyed in detail. The superiority of the CMOS-DRAM over the NMOS-DRAM is shown.