Reliability and performance tradeoffs in the design of on-chip power delivery and interconnects

被引：0

作者：

Taylor, Gregory F. ^{[1
]}

Arabi, Tawfik ^{[1
]}

Greub, Hans ^{[1
]}

Muyshondt, Richard ^{[1
]}

Manthe, Alicia ^{[1
]}

Aminzadeh, Payman ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, United States

来源：

IEEE Topical Meeting on Electrical Performance of Electronic Packaging | 1999年

关键词：

CMOS integrated circuits - Current density - Electric potential - Electromigration - Hot carriers - Integrated circuit layout - Oxides - Reliability;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The performance of CMOS integrated circuits has always been, and continues to be, limited by reliability considerations. Performance, reliability and cost are traded off through voltage and temperature specifications. The temperature acceleration of breakdown in oxides is increasing with decreasing thickness, current densities are increasing further stressing electromigration, inductive noise effects are becoming more significant while soft error susceptibility is increasing. In addition to all of these deleterious effects, oxide wear out has become a major factor in determining lifetime of very thin oxides. The design and validations issues associated with oxide wear out failure mechanisms are discussed.

引用

页码：49 / 52

共 50 条

[1] Power Delivery Design, Signal Routing and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes
Lanzillo, Nicholas A.
Chu, Albert
Bhosale, Prasad
Dechene, Dan
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 30 (01) : 60 - 67
[2] Evaluating Design Tradeoffs in On-Chip Power Management for CMPs
Sharkey, Joseph
Buyuktosunoglu, Alper
Bose, Pradip
ISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2007, : 44 - 49
[3] Performance evaluation and design tradeoffs of on-chip interconnect architectures
Bakhouya, M.
Suboh, S.
Gaber, J.
El-Ghazawi, T.
Niar, S.
SIMULATION MODELLING PRACTICE AND THEORY, 2011, 19 (06) : 1496 - 1505
[4] Design methodology for on-chip interconnects
Cases, M
Smith, H
Bowen, M
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 1998, : 27 - 30
[5] Performance Modeling for carbon nanotube interconnects in on-chip power distribution
Naeemi, Azad
Huang, Gang
Meindl, James D.
57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS, 2007, : 420 - +
[6] Analog/RF Design Techniques for High Performance Nanoelectronic On-Chip Interconnects
Liu, Bao
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 1823 - 1826
[7] Efficient power modeling for on-chip global interconnects
Aswatha, A. R.
Basavaraju, T.
Kalpana, A. B.
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2008, : 458 - +
[8] Distributed On-Chip Power Delivery
Koese, Selcuk
Friedman, Eby G.
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2012, 2 (04) : 704 - 713
[9] Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations
Kenarangi, Farid
Partin-Vaisband, Inna
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (02) : 769 - 781
[10] High-performance current mode receiver design for on-chip VLSI interconnects
Agrawal, Yash
Chandel, Rajeevan
Dhiman, Rohit
Advances in Intelligent Systems and Computing, 2015, 343 : 527 - 536

← 1 2 3 4 5 →