ON HIGH-SPEED PARALLEL ALGORITHMS USING REDUNDANT CODING.

被引:0
|
作者
Yasuura, Hiroto [1 ]
Takagi, Naofumi [1 ]
Tajima, Shuzo [1 ]
机构
[1] Kyoto Univ, Kyoto, Jpn, Kyoto Univ, Kyoto, Jpn
来源
Systems and Computers in Japan | 1987年 / 18卷 / 12期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:72 / 80
相关论文
共 50 条
  • [1] High-Speed Parallel Decimal Multiplication with Redundant Internal Encodings
    Han, Liu
    Ko, Seok-Bum
    IEEE TRANSACTIONS ON COMPUTERS, 2013, 62 (05) : 956 - 968
  • [2] Parallel architecture for high-speed LZSS data coding/decoding
    Fujioka, Toyota
    Aso, Hirotomo
    Systems and Computers in Japan, 2000, 31 (09) : 49 - 59
  • [3] High-speed redundant reciprocal approximation
    Seidel, PM
    INTEGRATION-THE VLSI JOURNAL, 1999, 28 (01) : 1 - 12
  • [4] A HIGH-SPEED MULTIPLIER USING A REDUNDANT BINARY ADDER TREE
    HARATA, Y
    NAKAMURA, Y
    NAGASE, H
    TAKIGAWA, M
    TAKAGI, N
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (01) : 28 - 34
  • [5] HIGH-SPEED PARALLEL COUNTER
    GUSKOV, BN
    KALINNIKOV, VA
    KRASTEV, VR
    MAKSIMOV, AN
    NIKITYUK, NM
    INSTRUMENTS AND EXPERIMENTAL TECHNIQUES, 1984, 27 (06) : 1397 - 1399
  • [6] Performance Analysis of a High-Speed Redundant Robot
    Callegari, Massimo
    Palmieri, Giacomo
    Palpacelli, Matteo-Claudio
    Bussola, Roberto
    Legnani, Giovanni
    2018 14TH IEEE/ASME INTERNATIONAL CONFERENCE ON MECHATRONIC AND EMBEDDED SYSTEMS AND APPLICATIONS (MESA), 2018,
  • [7] Parallel architecture for high-speed Lempel-Ziv data coding/decoding
    Fujioka, Toyota
    Aso, Hirotomo
    Systems and Computers in Japan, 1998, 29 (08) : 28 - 37
  • [8] A parallel scheme for implementing multialphabet arithmetic coding in high-speed programmable hardware
    Mahapatra, S
    Singh, K
    ITCC 2005: International Conference on Information Technology: Coding and Computing, Vol 1, 2005, : 79 - 84
  • [9] Distributed Parallel Scheduling Algorithms for High-Speed Virtual Output Queuing Switches
    Mhamdi, Lotfi
    Hamdi, Mounir
    ISCC: 2009 IEEE SYMPOSIUM ON COMPUTERS AND COMMUNICATIONS, VOLS 1 AND 2, 2009, : 944 - +
  • [10] High-speed pipelined DAC architecture using Gray coding
    Signell, Svante
    Shaber, Mezbah Uddin
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 113 - +