B. C. D. MULTIPLIERS.

被引：0

作者：

Webster, Max B

Baker, Paul W.

机构：

来源：

IEE Journal on Computers and Digital Techniques | 1979年 / 2卷 / 05期

关键词：

Compendex;

D O I：

10.1049/ij-cdt.1979.0049

中图分类号：

学科分类号：

摘要：

B. C. D. versions of known multiplier designs are presented; both achieve fast multiplication times without the high hardware cost typically associated with high speed. Serial b. c. d. addition and r. o. m. single-digit multipliers permit the substantial reductions in hardware cost, while higher clock frequencies offset the inherent slowness of the serial methods. Greatest cost-effectiveness is seen to be achieved through l. s. i. implementation of a serial design which is easily extended for higher radix b. c. d. multiplication.

引用

页码：226 / 230

页数：4