Implementations of continuous-time current-mode ladder filters using multiple output current integrators

Three different approaches to designing continuous-time current-mode ladder filters using multiple output current integrators are presented. These approaches are based on simulating node voltages, state variables, or loop currents of passive RLC ladder filter prototypes. Node voltage and state variable simulations yield more compact structures than that obtained using loop current simulation. Possible CMOS implementations are presented and their performance characteristics are investigated using SPICE simulations. Scaled filters, using the constant field scaling law, are found to operate properly at low supply voltages, down to 1.0 V.