Shared memory multistage clustering structure, an efficient structure for massively parallel processing systems

被引：0

作者：

Electrical Engineering Department, Iran University of Science and Technology, Narmak ^{[1
]}

Tehran

16844, Iran

不详 ^{[2
]}

VIC, Australia

机构：

来源：

Proc. - Int. Conf./Exhib. High Perform. Comput. Asia-Pac. Reg., HPC-Asia | / 22-27期

关键词：

Compendex;

D O I：

846510

中图分类号：

学科分类号：

摘要：

Queueing theory - Queueing networks - Parallel processing systems - Memory architecture

引用

共 4 条

[1] Performance analysis tools for parallel Java applications on shared-memory systems
European Center for Parallelism of Barcelona , Computer Architecture Department, Technical University of Catalonia, Campus Nord UPC, C/ Jordi Girona 1-3, Mòdul C6, Barcelona
E-08034, Spain
不详
EH9 3JZ, United Kingdom
Proc. Int. Conf. Parallel Process., 1600, (357-364):
[2] TECHNIQUES FOR MODELING PARALLEL SYSTEMS WITH DYNAMIC STRUCTURE
WILEDEN, JC
JOURNAL OF DIGITAL SYSTEMS, 1980, 4 (02): : 177 - 197
[3] A systems-information approach for setting up an efficient structure of dispatch control
Yusifbeili, N.A.
Elektr, 4 (15-18):
[4] Influence of the structure of the processor-memory-interconnection-system on the effiency of multiprocessor systems: The simulation approach
Both, R.
IT - Information Technology, 1981, 23 (1-6): : 107 - 115