Methodology of layout based schematic and its usage in efficient high performance CMOS design

As diffusion diodes and parasitic capacitance degrade CMOS circuit performance, the simulation results between schematic and its layout counterpart differ from each other because of the missing parasitic components in the schematic. This paper proposes a layout based schematic (LBS) method for high performance CMOS cell design. In this method, we introduce different types of MOS transistors and a wire capacitance estimation method, based on layout knowledge. The result of LBS is reliable and easy to be optimized during schematic procedure. The design time can be reduced from 2.5 to 10 times, according to our experience. It will reduce the design time and cost of high performance circuit design, and is much easier to be translated into a real layout than the original schematic.