Statistical design techniques for high-speed circuit boards with correlated structure distributions

被引：0
|
作者：
Mikazuki, Tetsuo [1 ]
Matsui, Norio [1 ]
机构：
[1] NTT Commun Switching Lab,, Musashino-shi, Tokyo, Japan
来源：
IEEE transactions on components, hybrids, and manufacturing technology | 1991年 / 14卷 / 03期
关键词：
Correlated structure distributions - Distributed circuit modes - Eye patterm simulation - High-speed circuit boards - Line parameter calculation - Monte Carlo simulation - Statistical design techniques;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：512 / 517
相关论文
共 50 条
  • [21] Analysis of via in multilayer printed circuit boards for high-speed digital systems
    Kim, JH
    Han, SW
    Kwon, OK
    ADVANCES IN ELECTRONIC MATERIALS AND PACKAGING 2001, 2001, : 382 - 387
  • [22] Design Techniques for High-Speed Wireline Transmitters
    Razavi, Behzad
    IEEE Open Journal of the Solid-State Circuits Society, 2021, 1 : 53 - 66
  • [23] Via Design Optimization for High Speed Differential Interconnects on Circuit Boards
    Vardapetyan, Armen
    Ong, Chong-Jin
    2020 IEEE 29TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS 2020), 2020,
  • [24] Analyze and Design High-Speed Power Delivery Networks Using New Multiinput Impedances in Printed Circuit Boards
    Zhang, Mu-Shui
    Li, Yu-Shan
    Li, Li-Ping
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2009, 57 (07) : 1818 - 1831
  • [25] Signal integrity analysis of the traces in electromagnetic-bandgap structure in high-speed printed circuit boards and packages
    Zhang, Mu-Shui
    Li, Yu-Shan
    Jia, Chen
    Li, Li-Ping
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2007, 55 (05) : 1054 - 1062
  • [26] High-Speed CMOS Track/Hold Circuit Design
    Haruo Kobayashi
    Mohd Asmawi Mohamed Zin
    Kazuya Kobayashi
    Hao San
    Hiroyuki Sato
    Jun-Ichi Ichimura
    Yoshitaka Onaya
    Yuuichi Takahashi
    Naoki Kurosawa
    Yasuyuki Kimura
    Yasushi Yuminaka
    Kouji Tanaka
    Takao Myono
    Fuminori Abe
    Analog Integrated Circuits and Signal Processing, 2001, 27 : 161 - 170
  • [27] High-speed CMOS Track/Hold circuit design
    Kobayashi, H
    Zin, MAM
    Kobayashi, K
    San, H
    Sato, H
    Ichimura, JI
    Onaya, Y
    Kurosawa, N
    Kimura, Y
    Yuminaka, Y
    Tanaka, K
    Myono, T
    Abe, F
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2001, 27 (1-2) : 161 - 170
  • [28] Multi-stack Technique for a Compact and Wideband EBG Structure in High-Speed Multilayer Printed Circuit Boards
    Kim, Myunghoi
    ETRI JOURNAL, 2016, 38 (05) : 903 - 910
  • [29] High-speed, robust CMOS dynamic circuit design
    Lai, Lianzhang
    Tang, Tingao
    Lin, Yinyin
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2006, 27 (06): : 1006 - 1011
  • [30] High-speed CORDIC implementations using advanced circuit techniques
    Jung, GN
    Kim, S
    Sobelman, GE
    2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING - VOL IV: SIGNAL PROCESSING FOR COMMUNICATIONS; VOL V: SIGNAL PROCESSING EDUCATION SENSOR ARRAY & MULTICHANNEL SIGNAL PROCESSING AUDIO & ELECTROACOUSTICS; VOL VI: SIGNAL PROCESSING THEORY & METHODS STUDENT FORUM, 2001, : 1237 - 1240
12345