A RISC architecture for symbolic computation

被引：0

作者：

Kieburtz, Richard B. ^{[1
]}

机构：

[1] Oregon Graduate Center, 19600N.W. von Neumann Dr., Beaverton,OR,97006, United States

来源：

Operating Systems Review (ACM) | 1987年 / 21卷 / 04期

关键词：

Cache memory - Directed graphs - Pipeline processing systems - Reduced instruction set computing;

D O I：

10.1145/36204.36197

中图分类号：

学科分类号：

摘要：

The G-machine is a language-directed processor architecture designed to support graph reduction as a model of computation. It can carry out lazy evaluation of functional language programs and can evaluate programs in which logical variables are used. To support these language features, the abstract machine requires tagged memory and executes some rather complex instructions, such as to evaluate a function application.This paper explores an implementation of the G-machine as a high performance RISC architecture. Complex instructions can be represented by RISC code without experiencing a large expansion of code volume. The instruction pipeline is discussed in some detail. The processor is intended to be integrated into a standard, 32-bit memory architecture. Tagged memory is supported by aggregating data with tags in a cache. © 1987 Copyright is held by the owner/author(s).

引用

页码：146 / 155