New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array

被引：0

作者：

Hsiao, Shen-Fu ^{[1
]}

Shiue, Wei-Ren ^{[1
]}

机构：

[1] Natl Sun Yat-Sen Univ, Kaohsiung, Taiwan

来源：

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | 1999年 / 6卷

关键词：

Computational complexity - Fast Fourier transforms - Matrix algebra - Systolic arrays - VLSI circuits;

D O I：

暂无

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学科分类号：

摘要：

A new recursive algorithm for fast computation of two-dimensional discrete cosine transforms (2-D DCT) is derived by converting the 2-D data matrices into 1-D vectors and then using different partition methods for the time and frequency indices. The algorithm first computes the 2-D complex DCT (2-D CCT) and then produces two 2-D DCT outputs simultaneously through a post-addition step. The decomposed form of the 2-D recursive algorithm looks very like a radix-4 FFT algorithm and is in particular suitable for VLSI implementation since the common entries in each row of the butterfly-like matrix are factored out in order to reduce the number of multipliers. A new linear systolic architecture is presented which leads to a hardware-efficient architectural design requiring only logN multipliers plus 3logN adders/subtractors for the computation of two N×N DCTs.

引用

页码：3517 / 3520