SOI technology for sub-0.25 μm CMOS

被引：0

作者：

Maszara, W.P. ^{[1
]}

机构：

[1] SEMATECH, Sunnyvale, United States

来源：

Electron Technology (Warsaw) | 1999年 / 32卷 / 01期

关键词：

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

页码：16 / 20

共 50 条

[31] Advanced LPCVD BPSG deposition for sub-0.25 mu m microelectronic fabrication [J].

Ilg, M ;

Kirchhoff, M ;

Nguyen, S .

PROCEEDINGS OF THE THIRTEENTH INTERNATIONAL CONFERENCE ON CHEMICAL VAPOR DEPOSITION, 1996, 96 (05) :863-868

[32] Critical dimension control optimization methodology on shallow trench isolation substrate for sub-0.25 μm technology gate patterning [J].

Fan, MH ;

Gerung, H ;

Yelehanka, PR ;

Cheng, A ;

Zhou, MS ;

Chi, C ;

Tan, CH ;

Xie, J .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2001, 19 (02) :456-460

[33] Optimizing sputtered TiN ARC film properties for lithography of sub-0.25μm interconnect [J].

Sengupta, SS ;

Baker, D ;

Sethi, S ;

Bothra, S .

ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 :539-546

[34] High aspect ratio Bosch etching of sub-0.25 μm trenches for hyperintegration applications [J].

Wang, Xiaodong ;

Zeng, Wanxue ;

Lu, Guoping ;

Russo, Onofrio L. ;

Eisenbraun, Eric .

JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2007, 25 (04) :1376-1381

[35] Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 μm partially depleted SOI MOSFETs [J].

Matsumoto, T ;

Maeda, S ;

Hirano, Y ;

Eikyu, K ;

Yamaguchi, Y ;

Maegawa, S ;

Inuishi, M ;

Nishimura, T .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (01) :55-60

[36] 0.25μm radiation tolerant CMOS technology [J].

Roedde, K .

PROCEEDINGS OF THE EUROPEAN SPACE COMPONENTS CONFERENCE - ESCCON 2002, 2002, 507 :31-33

[37] 0.25 μm CMOS/SIMOX device technology [J].

NTT Rev, 4 (78-87)

[38] 0.25 μm CMOS/SIMOX device technology [J].

Tsuchiya, Toshiaki ;

Ohno, Terukazu ;

Kado, Yuichi ;

Nakashima, Sadao .

NTT R and D, 1997, 46 (04) :361-370

[39] High aspect ratio silicon trench etching for sub-0.25 μm device applications [J].

Ranade, RM ;

Mathad, GS .

PLASMA ETCHING PROCESSES FOR SUB-QUARTER MICRON DEVICES, PROCEEDINGS, 2000, 99 (30) :193-199

[40] Implementation of a closed-loop CD and overlay controller for sub-0.25 μm patterning [J].

Sturtevant, J ;

Weilemann, M ;

Green, K ;

Dwyer, J ;

Robertson, E ;

Hershey, R .

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XII, 1998, 3332 :461-470

← 1 2 3 4 5 →