Discrete-time queueing models with feedback for input-buffered ATM switches

被引:0
作者
Laevens, K. [1 ]
Bruneel, H. [1 ]
机构
[1] Univ of Ghent, Ghent, Belgium
来源
Performance Evaluation | 1996年 / 27-28卷
关键词
D O I
暂无
中图分类号
学科分类号
摘要
20
引用
收藏
页码:71 / 87
相关论文
共 50 条
[21]   A new packet scheduling algorithm for input-buffered multicast packet switches [J].
Liu, NH ;
Yeung, KL .
GLOBECOM 97 - IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, CONFERENCE RECORD, VOLS 1-3, 1997, :1695-1699
[22]   Researches on window access schemes for input-buffered ATM switching fabrics [J].
Liu, Yashe ;
Liu, Zengji ;
Hu, Zheng .
Tien Tzu Hsueh Pao/Acta Electronica Sinica, 1998, 26 (01) :38-42
[23]   An analytical model for input-buffered optical packet switches with reconfiguration overhead [J].
Chou, Kuan-Hung ;
Lin, Woei .
PHOTONIC NETWORK COMMUNICATIONS, 2011, 22 (03) :209-220
[24]   Stability analysis of input-buffered packet switches with maximal size matching [J].
Han, MS ;
Kim, B .
IEEE COMMUNICATIONS LETTERS, 2005, 9 (05) :462-464
[25]   Performance analysis of lookahead scheduling algorithm for input-buffered packet switches [J].
Yeung, KL ;
Shi, H ;
Liu, NH .
IEICE TRANSACTIONS ON COMMUNICATIONS, 1999, E82B (08) :1296-1303
[26]   A fair queueing architecture for ATM switches with input buffers [J].
Shimojo, Y .
IEEE GLOBECOM 1996 - CONFERENCE RECORD, VOLS 1-3: COMMUNICATIONS: THE KEY TO GLOBAL PROSPERITY, 1996, :830-834
[27]   Analysis of Input and Output Queueing for Nonblocking ATM Switches [J].
Pattavina, Achille ;
Bruzzi, Giacomo .
IEEE-ACM TRANSACTIONS ON NETWORKING, 1993, 1 (03) :314-328
[28]   MNCM a new class of efficient scheduling algorithms for input-buffered switches with no speedup [J].
Tabatabaee, V ;
Tassiulas, L .
IEEE INFOCOM 2003: THE CONFERENCE ON COMPUTER COMMUNICATIONS, VOLS 1-3, PROCEEDINGS, 2003, :1406-1413
[29]   Generalization of the Pollaczek-Khinchin formula for throughput analysis of input-buffered switches [J].
Chang, CS ;
Lee, DS ;
Yu, CL .
IEEE INFOCOM 2005: THE CONFERENCE ON COMPUTER COMMUNICATIONS, VOLS 1-4, PROCEEDINGS, 2005, :960-970
[30]   Neural parallel-hierarchical-matching scheduler for input-buffered packet switches [J].
González-Castaño, FJ ;
López-Bravo, C ;
Asorey-Cacheda, R ;
Pousada-Carballo, JM ;
Rodríguez-Hernández, PS .
IEEE COMMUNICATIONS LETTERS, 2002, 6 (05) :220-222