Twisted differential transmission line structure for global interconnect in Si LSI

被引:0
作者
Ito, Hiroyuki [1 ]
Gomi, Shinichiro [1 ]
Sugita, Hideyuki [1 ]
Okada, Kenichi [1 ]
Masu, Kazuya [1 ]
机构
[1] Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
来源
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2005年 / 44卷 / 4 B期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
12
引用
收藏
页码:2774 / 2779
相关论文
共 50 条
[11]   Pseudo differential transmission line structure on SiULSI [J].
Sugita, H ;
Ito, H ;
Gomi, S ;
Okada, K ;
Masu, K .
ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, :165-170
[12]   A low-power differential transmission line interconnect using wafer level package technology [J].
Maekawa, Tomoaki ;
Ishii, Takahiro ;
Seita, Junki ;
Ito, Hiroyuki ;
Okada, Kenichi ;
Hatakeyama, Hideki ;
Uemichi, Yusuke ;
Aizawa, Takuya ;
Ito, Tatsuya ;
Yamauchi, Ryozo ;
Masu, Kazuya .
2008 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS, 2008, :99-+
[13]   On-chip Differential-Transmission-Line(DTL) interconnect for 22nm technology [J].
Okada, Kenichi ;
Ito, Hiroyuki ;
Masu, Kazuya .
ADVANCED METALLIZATION CONFERENCE 2006 (AMC 2006), 2007, :29-33
[14]   A novel twisted differential line on PCB: Crosstalk model and its application to high-speed interconnect circuit design [J].
Kam, DG ;
Kim, JG .
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2002, :153-156
[15]   Optimization methodology of global interconnect structure [J].
Inoue, J ;
Nakashima, H ;
Kyogoku, T ;
Uezono, T ;
Okada, K ;
Masu, K .
16TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, 2004, :351-354
[16]   TWISTED MAGNET WIRE TRANSMISSION-LINE [J].
LEFFERSON, P .
IEEE TRANSACTIONS ON PARTS HYBRIDS AND PACKAGING, 1971, PHP7 (04) :148-+
[17]   Design Methodology of High Performance On-Chip Global Interconnect Using Terminated Transmission-Line [J].
Zhang, Yulei ;
Zhang, Ling ;
Deutsch, Alina ;
Katopis, George A. ;
Dreps, Daniel M. ;
Buckwalter, James F. ;
Kuh, Ernest S. ;
Cheng, Chung-Kuan .
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, :451-+
[18]   Reduction of Transmission Line Losses Using VLSI Interconnect [J].
Abbasi, Ruby .
INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011, 2012, 30 :10-19
[19]   High speed and low power globel interconnect IP with differential transmission line and driver-receiver circuits [J].
Gomi, S ;
Nakamura, K ;
Ito, H ;
Okada, K ;
Masu, K .
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, :384-387
[20]   Transmission line Model for inherently stable MSWCNT bundled global interconnect for 22nm Technology Node [J].
Mishra, Shailendra ;
Mishra, Divya .
2017 4TH IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS (UPCON), 2017, :184-190