共 50 条
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Pseudo differential transmission line structure on SiULSI
[J].
ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004),
2004,
:165-170
[12]
A low-power differential transmission line interconnect using wafer level package technology
[J].
2008 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS,
2008,
:99-+
[13]
On-chip Differential-Transmission-Line(DTL) interconnect for 22nm technology
[J].
ADVANCED METALLIZATION CONFERENCE 2006 (AMC 2006),
2007,
:29-33
[14]
A novel twisted differential line on PCB: Crosstalk model and its application to high-speed interconnect circuit design
[J].
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING,
2002,
:153-156
[15]
Optimization methodology of global interconnect structure
[J].
16TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS,
2004,
:351-354
[16]
TWISTED MAGNET WIRE TRANSMISSION-LINE
[J].
IEEE TRANSACTIONS ON PARTS HYBRIDS AND PACKAGING,
1971, PHP7 (04)
:148-+
[17]
Design Methodology of High Performance On-Chip Global Interconnect Using Terminated Transmission-Line
[J].
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2,
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Reduction of Transmission Line Losses Using VLSI Interconnect
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INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY AND SYSTEM DESIGN 2011,
2012, 30
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[19]
High speed and low power globel interconnect IP with differential transmission line and driver-receiver circuits
[J].
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS,
2004,
:384-387
[20]
Transmission line Model for inherently stable MSWCNT bundled global interconnect for 22nm Technology Node
[J].
2017 4TH IEEE UTTAR PRADESH SECTION INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND ELECTRONICS (UPCON),
2017,
:184-190