Multiple-bit-rate clock recovery circuit: theory

被引:0
|
作者
Conductus, Inc., 969 West Maude Ave, Sunnyvale, CA 94086, United States [1 ]
机构
来源
Supercond Sci Technol | / 11卷 / 925-928期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [41] A clock and data recovery PLL for variable bit rate NRZ data using adaptive phase frequency detector
    Idei, GJ
    Kunieda, H
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06): : 956 - 963
  • [42] Phase detector for data-clock recovery circuit
    Hati, A
    Ghosh, M
    Sarkar, BC
    ELECTRONICS LETTERS, 2002, 38 (04) : 161 - 163
  • [43] A novel clock recovery circuit for fully monolithic integration
    Murata, K
    Otsuji, T
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1999, 47 (12) : 2528 - 2533
  • [44] A novel clock recovery circuit for fully monolithic integration
    Murata, K
    Otsuji, T
    1999 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-4, 1999, : 201 - 204
  • [45] A 5-Gb/s 1/8-rate CMOS clock and data recovery circuit
    Kwon, JK
    Heo, TK
    Cho, SB
    Park, SM
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 293 - 296
  • [46] A 7 GB/S HALF-RATE CLOCK AND DATA RECOVERY CIRCUIT WITH COMPACT CONTROL LOOP
    Cheng, Yu-Po
    Lee, Yen-Long
    Chien, Ming-Hung
    Chang, Soon-Jyh
    2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2016,
  • [47] A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique
    Weng, Jun-Hong
    Tsai, Meng-Ting
    Lin, Jung-Mao
    Yang, Ching-Yuan
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 3073 - +
  • [48] Clock recovery for circuit emulation services over ATM
    CastelBranco, L
    Nunes, MS
    BROADBAND COMMUNICATIONS: GLOBAL INFRASTRUCTURE FOR THE INFORMATION AGE, 1996, : 617 - 625
  • [49] A CMOS clock and data recovery circuit with a half-rate three-state phase detector
    Yang, Ching-Yuan
    Lee, Yu
    Lee, Cheng-Hsing
    IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (06): : 746 - 752
  • [50] A Half-Rate 100 Gb/s Injection-Locked Clock/Data Recovery Circuit
    Samavaty, Behzad
    Green, Michael M.
    2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2016,