SIGNAL DELAY CALCULATION FOR INTEGRATED CMOS CIRCUITS.

This paper presents a new approach to the calculation of signal delays for integrated CMOS circuits. The approach is based on a functional characterization of basic cells with respect to their delay properties. Output load, signal waveforms and operating conditions are considered for the delay calculation at gate level. The impact of the physical layout on the dynamic performance of the circuit is derived from a RC representation of the routing paths. The accuracy and efficiency of the approach is shown by comparing its predicted timing results to measured data for a gate array application.