Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication

被引：0
|
作者：
Zimmermann, Reto [1 ]
机构：
[1] Swiss Federal Inst of Technology, (ETH), Zurich, Switzerland
来源：
Proceedings - Symposium on Computer Arithmetic | 1999年
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
17
引用
收藏
页码：158 / 167
相关论文
共 50 条
  • [21] Efficient VLSI Implementation for Montgomery Multiplication in GF(2(m))
    Chiou, Che-Wun
    Lee, Chiou-Yng
    Deng, An-Wen
    Lin, Jim-Min
    JOURNAL OF APPLIED SCIENCE AND ENGINEERING, 2006, 9 (04): : 365 - 372
  • [22] On the design of modulo 2n±1 adders
    Efstathiou, C
    Vergos, HT
    Nikolos, D
    ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 517 - 520
  • [23] A VLSI programmable cellular automats array for multiplication in GF(2n)
    Zhang, CN
    Deng, MY
    Mason, R
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, PROCEEDINGS, 1999, : 1118 - 1123
  • [24] Modulo M multiplication-addition:: algorithms and FPGA implementation
    Beuchat, J
    Muller, JM
    ELECTRONICS LETTERS, 2004, 40 (11) : 654 - 655
  • [25] EFFICIENT METHOD FOR DESIGNING MODULO {2n ± k} MULTIPLIERS
    Pettenghi, Hector
    Cotofana, Sorin
    Sousa, Leonel
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2014, 23 (01)
  • [26] Algorithm for modulo (2n+1) multiplication
    Sousa, LA
    ELECTRONICS LETTERS, 2003, 39 (09) : 752 - 754
  • [27] Designing of area and power efficient modulo 2N multiplier
    Shalini, R. V.
    Sampath, P.
    2014 3RD INTERNATIONAL CONFERENCE ON ECO-FRIENDLY COMPUTING AND COMMUNICATION SYSTEMS (ICECCS 2014), 2014, : 246 - 249
  • [28] Weight of an n-dimensional Boolean vector and addition modulo 2n; The generalization to the case of modulo mn
    Sevastyanov, B.A.
    Discrete Mathematics and Applications, 5 (04):
  • [29] Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS
    Muralidharan, Ramya
    Chang, Chip-Hong
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (10) : 2263 - 2274
  • [30] Efficient new approach for modulo 2n-1 addition in RNS
    Patel, R. A.
    Benaissa, M.
    Boussakta, S.
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2006, 153 (06): : 399 - 405
12345