Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication

被引:0
|
作者
Zimmermann, Reto [1 ]
机构
[1] Swiss Federal Inst of Technology, (ETH), Zurich, Switzerland
关键词
D O I
暂无
中图分类号
学科分类号
摘要
17
引用
收藏
页码:158 / 167
相关论文
共 50 条
  • [1] Efficient VLSI implementation of module (2n±1) addition and multiplication
    Zimmermann, R
    14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, : 158 - 167
  • [2] REGULAR VLSI ARCHITECTURES FOR MULTIPLICATION MODULO (2N + 1)
    CURIGER, AV
    BONNENBERG, H
    KAESLIN, H
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (07) : 990 - 994
  • [3] Vlsi implementation of modulo multiplication using carry free addition
    Sarkar, P
    Roy, BK
    Choudhury, PP
    TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 457 - 460
  • [4] Regular time-efficient VLSI architecture for multiplication modulo 2n+1
    Zhou, Haohua
    Li, Zhiyong
    Xie, Wenlu
    Zhang, Qianling
    Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2000, 21 (10): : 1032 - 1037
  • [5] Efficient modulo 2n ± 1 squarers
    Bakalis, D.
    Vergos, H. T.
    Spyrou, A.
    INTEGRATION-THE VLSI JOURNAL, 2011, 44 (03) : 163 - 174
  • [6] An Efficient 2n RNS Scaler and Its VLSI Implementation
    Ma, Shang
    Hu, Jianhao
    Zhang, Lin
    Ling, Xiang
    2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEM, 2008, : 1498 - 1501
  • [7] Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n-1, 2n, 2n+1}
    Tay, Thian Fatt
    Chang, Chip-Hong
    Low, Jeremy Yung Shern
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (10) : 1936 - 1940
  • [8] High -Performance Multiplication Modulo 2n - 3
    Seidel, Peter-Michael
    2018 CONFERENCE RECORD OF 52ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 2018, : 130 - 134
  • [9] Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS {2n - 1, 2n, 2n + 1} (vol 21, pg 1936, 2013)
    Tay, Thian Fatt
    Chang, Chip-Hong
    Low, Jeremy Yung Shern
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (04) : 1612 - 1612
  • [10] An efficient tree architecture for modulo 2(n)+1 multiplication
    Wang, ZD
    Jullien, GA
    Miller, WC
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1996, 14 (03): : 241 - 248