共 50 条
- [1] Efficient VLSI implementation of module (2n±1) addition and multiplication 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, : 158 - 167
- [3] Vlsi implementation of modulo multiplication using carry free addition TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 457 - 460
- [4] Regular time-efficient VLSI architecture for multiplication modulo 2n+1 Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2000, 21 (10): : 1032 - 1037
- [6] An Efficient 2n RNS Scaler and Its VLSI Implementation 2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEM, 2008, : 1498 - 1501
- [8] High -Performance Multiplication Modulo 2n - 3 2018 CONFERENCE RECORD OF 52ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 2018, : 130 - 134
- [10] An efficient tree architecture for modulo 2(n)+1 multiplication JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1996, 14 (03): : 241 - 248