Intra-level mix-and-match lithography process for fabricating sub-100-nm complementary metal-oxide-semiconductor devices using the JBX-9300FS point-electron-beam system

To increase the throughput of electron beam lithography used to fabricate sub-100-nm patterns, we developed an electron beam and deep UV intra-level mix-and-match lithography process, that uses the JBX-9300FS point-electron-beam system and a conventional KrF stepper. Pattern data preparation was improved for sub-100-nm patterns. To reduce the effect of line width variation caused by post-exposure delay on complementary metal-oxide-semiconductor (CMOS) devices, we first exposed KrF patterns and then added another post-exposure bake before the electron beam (EB) exposure. We have used this technique to expose the gate layer of sub-100-nm CMOS devices. When we set the threshold size between EB and KrF patterns at 0.16 μm, the throughput of electron beam lithography was about threefold that of the full exposure by the electron beam lithography process. Sub-50-nm CMOS devices with high drive current were successfully fabricated.