Scalable, real-time, image processing pipeline

被引：0

作者：

Delft Univ of Technology, Delft, Netherlands ^{[1
]}

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来源：

Mach Vision Appl | / 2卷 / 110-121期

关键词：

CMOS integrated circuits - Computer vision - Inspection - Mathematical morphology - Real time systems - Robots - VLSI circuits;

D O I：

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摘要：

To speed up image processing in the field of robot vision and industrial inspection, a pipeline element that can perform fast cellular logic operations was made. This cellular logic processing element (CLPE) can process binary images with a speed of 100 ns per pixel. The processing element is a CMOS VLSI device. It includes a writable logic array for storing sets of 3×3 structuring elements that define the cellular logic operations. This paper describes how such CLPEs can be used for building a pipeline for mixed gray-value processing and cellular logic processing.

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