TAKE THE GUESSWORK OUT OF PHASE LOCKED LOOP DESIGN.

被引：0
作者：
Kesner, Don
机构：
来源：
EDN | 1973年 / 18卷 / 01期
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D O I：
暂无
中图分类号：
TN7 [基本电子电路];
学科分类号：
080902 ;
摘要：
Phase locked loop (PLL) systems are being used today in an ever-increasing number and variety of applications. However, many users still encounter problems which they do not fully understand. These problems usually fall into two basic areas: dynamic peculiarities, such as excessive overshoot, ringing and extended settling time; and spectral-purity problems associated with sideband suppression, which is a problem particularly apparent in digital frequency synthesizers. This article discusses these two problems and provides a number of suggestions which may be used to avoid them.
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页码：54 / 60
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