Method for analytically determining the signature in self-testing LSSD structures

In the organization of VLSI self-testing using compact methods an important question is the reliability of test experiments. Workers should have a means of estimating the detecting power of the fixed and analyzed parts for possible circuit faults. The existing methods - computer and physical modeling - involve large costs. In the present work we have proposed a new analytical approach to self-testing of VLSI with LSSD structures whose fixed part is a generator of pseudorandom test vectors (PRTVG) and a compression structure (signature analyzer).