New dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS drams

被引：0

作者：

Wu, Chung-Yu ^{[1
]}

Yu-Yee, Liow ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Hsing Chu, Taiwan

来源：

Proceedings - IEEE International Symposium on Circuits and Systems | 1999年 / 1卷

关键词：

Amplifiers (electronic) - CMOS integrated circuits - Computer simulation - Integrated circuit manufacture - MOSFET devices - Performance - Threshold voltage;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A novel 1.5-bit (3-level)/cell storage technique is described. This sense amplifier of DRAM can sense the ternary state. Thus, this structure can effectively reduce the bit-cost. The proposed DRAM can be operated at 1.5V without changing the common DRAM process.

引用

共 32 条

[31] A low-power 10-bit CCP-based pipelined ADC using a multi-level variable current source MDAC and an ultra-low-power double-tail dynamic latch
Firouzkouhi, Hossein
Ashraf, Mohammadreza
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2021, 49 (03) : 830 - 852
[32] 0.8V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems
Shen, E
Kuo, JB
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS, 2002, : 583 - 586

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